1. Field
This disclosure relates generally to data processors, and more specifically, to the execution of branch and loop instructions by data processors.
2. Related Art
Branch target buffers have been used to improve processor performance by reducing the number of cycles spent in execution of branch instructions. Branch target buffers act as a cache of recent branches and accelerate branches by providing either a branch target address (address of the branch destination) or one or more instructions at the branch target prior to execution of the branch instruction, which allows a processor to more quickly begin execution of instructions at the branch target address.
Branch lookahead schemes are also used to accelerate branch processing, and operate by scanning ahead into the sequential instruction stream, looking for upcoming branch instructions in advance of their execution, and computing branch target addresses of branches early, to allow branch target instructions to be fetched in advance of branch instruction execution, in case the branch is taken.
Branch prediction logic may be used with both BTB and branch lookahead schemes to allow for an early prediction of the outcome (taken or not taken) of a conditional branch, prior to the resolution of the branch condition, thus allowing for increased branch performance when accuracy of the predictor is high.
As the number of pipeline stages within the data processing systems increases, the size of the branch target buffer (BTB) is typically increased in order to increase the hit rate and reduce the branch misprediction performance penalty. However, increasing the size of the BTB results in increased die area, access time, and power required for the BTB and its operation. Additionally, as the number of pipeline stage increases, the branch misprediction penalty increases. For the hard to predict branches, the increase in misprediction penalty will degrade performance of the processing system.